Browsing by Subject "Field programmable gate arrays (FPGA)"
Now showing items 1-5 of 5
-
Article
Architectural support for data-driven execution
(2014)The exponential growth of sequential processors has come to an end, and thus, parallel processing is probably the only way to achieve performance growth. We propose the development of parallel architectures based on ...
-
Conference Object
Energy efficient stream-based configurable architecture for embedded platforms
(2012)Reconfigurable hardware can be used as an energy and performance efficient co-processing solution to accelerate certain types of applications. To facilitate the design of hardware accelerators we have proposed a methodology ...
-
Conference Object
Implementation of IEEE single precision floating point addition and multiplication on FPGAs
(Affiliation: Rutgers Univ, Piscataway, United StatesCorrespondence Address: Louca, LoucasRutgers Univ, Piscataway, United States, 1996)Floating point operations are hard to implement on FPGAs because of the complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high levels of accuracy in their ...
-
Article
Rapid prototyping of the data-driven chip-multiprocessor (D 2-CMP) using FPGAs
(2008)This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that ...
-
Conference Object
Verilog-based simulation of hardware support for Data-flow concurrency on Multicore systems
(IEEE Computer Society, 2013)Data-Driven Multithreading (DDM) is a threaded data-flow model that schedules threads for execution based on data availability. DDM is utilizing a Thread Scheduling Unit (TSU) for the management of the threads on sequential ...